Abstract：In this paper, the problem of high power consumption and high cost for test are studied and analyzed. Taking a multiply-add as an example, which can switch between three working states: multiply, add and multiply-add. In the chip design process, the unified power format technology is used to achieve multi-voltage design to achieve low power consumption, and the scan chain technology is used to complete the design for test, reducing the test cost of the chip and solving the compatibility issues of the two technologies.
向韬鑫, 王仁平, 刘东明, 陈荣林. 多电压与扫描链技术在芯片设计中的应用研究[J]. 电气技术, 2020, 21(6): 35-38.
Xiang Taoxin, Wang Renping, Liu Dongming, Chen Ronglin. Research on application of multi-voltage and scan chain technology in chip design. Electrical Engineering, 2020, 21(6): 35-38.
2020, Vol. 21 
