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| The effect of gate low voltage on the turn-off transients |
| Li Lele1, Li Jiancheng2, Wang Hongli1, Sun Mingze1 |
1. College of Physics and Optoelectronic Engineering, Xiangtan University, Xiangtan, Hu’nan 411100;
2. School of Electronic Science and Engineering, National University of Defense Technology, Changsha 410073 |
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Abstract With the increase of switching frequency, the effect of parasitic inductance on silicon carbide (SiC) MOSFETs becomes more and more obvious, and crosstalk and device stress caused by the devices seriously restrict the application of SiC MOSFET devices under high frequency. In the actual design of the driver circuit, in order to suppress the crosstalk of the device, the gate low voltage is generally selected between -5~0V. However, the influence of low gate voltage on device stress is ignored. In this paper, through theoretical and simulation analysis, the overshoot voltage and power loss at turn-off transients at different gate voltages are studied in the presence of the parasitic inductance. Thus, in the design of the SiC MOSFET driver circuit, the selection of the gate low voltage is instructed.
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Received: 15 November 2018
Published: 16 November 2018
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2018, Vol. 19 
