Abstract In this paper, the problem of high power consumption and high cost for test are studied and analyzed. Taking a multiply-add as an example, which can switch between three working states: multiply, add and multiply-add. In the chip design process, the unified power format technology is used to achieve multi-voltage design to achieve low power consumption, and the scan chain technology is used to complete the design for test, reducing the test cost of the chip and solving the compatibility issues of the two technologies.
Xiang Taoxin,Wang Renping,Liu Dongming等. Research on application of multi-voltage and scan chain technology in chip design[J]. Electrical Engineering, 2020, 21(6): 35-38.
2020, Vol. 21 
