全国产化芯片继电保护装置可靠性测试关键技术研究及应用

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Abstract Based on the characteristics of the fully domesticated chip relay protection device's software and hardware platforms, and addressing the key and difficult points in the testing process, this paper proposes a multi-CPU internal communication testing method for fully domesticated chip relay protection devices. Utilizing a dedicated internal detection module, the method simulates and monitors various normal and abnormal data without altering the original wiring layout, to verify the stability of internal communications between CPU boards. Additionally, this paper presents key technologies of internal communication reliability testing and platform application testing, details test plans for critical applications such as platform self-check, intelligent IO self-check, abnormal reset functions, and memory overflow risks, and summarizes typical on-site problem verification and key testing items. Finally, by comparing and analyzing the differences in key technical indicators between the “nine unified” devices and fully domesticated chip relay protection devices, the study offers insights for the product development of fully domesticated chip relay protection devices.

Key words： fully domesticated chip relay protection abnormal simulation reliability

Received: 02 December 2024

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	Articles by authors
	ZHANG Wen
	MA Quanxia
	WANG Zhe
	HE Renke

Cite this article:

ZHANG Wen,MA Quanxia,WANG Zhe等. Research and application of key technologies for reliability testing of fully domesticated chip relay protection devices[J]. Electrical Engineering, 2025, 26(6): 68-74.

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https://dqjs.cesmedia.cn/EN/Y2025/V26/I6/68

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