锡盟—泰州特高压直流输电工程受端串联阀组中点分压器电压采集异常解决策略

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Abstract This paper describes the abnormal oscillation of the U_dM (midpoint divider in series valve group) voltage acquisition during the commissioning period of the XiMeng-TaiZhou UHVDC transmission project B station. According to the actual application and hardware configuration of the project, the problem is analyzed by tracing the data acquisition link. The main reason is that the valve group measurement layer is sampled at multiple frequencies, resulting in the signal aliasing phenomenon. In view of the problem, three strategies and concrete implementation methods are proposed, and the method of adding filter before sampling in the valve set is chosen in combination with the actual situation of the project. Filter using IIR digital filter, implement filter algorithm inside FPGA. After the implementation of the method, a large number of engineering tests were carried out, the U_dM acquisition anomaly was effectively solved and the engineering operation was stable.

Key words： ultra high-voltage direct current (UHVDC) signal aliasing field programmable gate array (FPGA) infinite impulse response (IIR) digital filter

Received: 19 November 2019

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	Articles by authors
	Guo Hufeng
	Zhang Wuyue
	Liu Xiao
	Lan Lan

Cite this article:

Guo Hufeng,Zhang Wuyue,Liu Xiao等. Cause analysis and countermeasures for U_dM collection abnormal in Ximeng-Taizhou UHVDC project B station[J]. Electrical Engineering, 2020, 21(6): 73-77.

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http://dqjs.cesmedia.cn/EN/Y2020/V21/I6/73

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