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| Design of teaching experiment for hardware acceleration system based on field programmable gate array |
| GAO Jiabao, SU Ting |
| School of Information and Communication Engineering, Hainan University, Haikou 570228 |
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Abstract Electronic design automation (EDA) technology course is a professional, applied and practical course for electronic communication majors in universities. Field programmable gate array (FPGA) with programmability and flexibility, as the hardware carrier of the course, can be applied to realizing complex systems and complex algorithms, and has excellent performance in various fields such as artificial intelligence, communication and medicine. To address the lack of systematic and hardware- software co-design in existing EDA course experiments, the research of the experiment teaching combining FPGA and artificial intelligence algorithms is carried out, and the design ability of the system-level and software-hardware coordination is cultivated by designing the FPGA-based neural network hardware acceleration system, which has certain reference significance for the FPGA experiment and the FPGA course design of the electronic information majors.
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Received: 05 November 2025
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| Cite this article: |
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GAO Jiabao,SU Ting. Design of teaching experiment for hardware acceleration system based on field programmable gate array[J]. Electrical Engineering, 2026, 27(6): 49-53.
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https://dqjs.cesmedia.cn/EN/Y2026/V27/I6/49
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2026, Vol. 27 
